Flips-Flops Questions and Answers
Flip-Flops are the fundamental building blocks of sequential logic circuits used in counters, memory, and data storage. This topic presents digital electronics aptitude questions and answers covering SR, JK, D, and T flip-flops with detailed explanations. Essential for GATE, DRDO, and BEL exam preparation, these MCQs help learners understand timing diagrams, truth tables, and applications in system design. By practicing these Flip-Flops questions with answers, you can master one of the most scoring areas in electronics and digital logic design.
Flips-Flops
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64 questions
21. A J-K flip-flop is in a "no change" condition when ________.
- J = 1, K = 1
- J = 1, K = 0
- J = 0, K = 1
- J = 0, K = 0
22. A correct output is achieved from a master-slave J-K flip-flop only if its inputs are stable while the:
- clock is LOW
- slave is transferring
- flip-flop is reset
- clock is HIGH
23. Which of the following describes the operation of a positive edge-triggered D flip-flop?
- If both inputs are HIGH, the output will toggle.
- The output will follow the input on the leading edge of the clock.
- When both inputs are LOW, an invalid state exists
- The input is toggled into the flip-flop on the leading edge of the clock and is passed to the output on the trailing edge of the clock.
24. What does the triangle on the clock input of a J-K flip-flop mean?
- level enabled
- edge-triggered
25. A J-K flip-flop with J = 1 and K = 1 has a 20 kHz clock input. The Q output is ________.
- constantly LOW
- constantly HIGH
- a 20 kHz square wave
- a 10 kHz square wave
26. The toggle condition in a master-slave J-K flip-flop means that Q and will switch to their ________ state(s) at the ________.
- opposite, active clock edge
- inverted, positive clock edge
- quiescent, negative clock edge
- reset, synchronous clock edge
27. On a positive edge-triggered S-R flip-flop, the outputs reflect the input condition when ________.
- the clock pulse is LOW
- the clock pulse is HIGH
- the clock pulse transitions from LOW to HIGH
- the clock pulse transitions from HIGH to LOW
28. What is the hold condition of a flip-flop?
- both S and R inputs activated
- no active S or R input
- only S is active
- only R is active
29. If an active-HIGH S-R latch has a 0 on the S input and a 1 on the R input and then the R input goes to 0, the latch will be ________.
- SET
- RESET
- clear
- invalid