Flips-Flops Questions and Answers
Flip-Flops are the fundamental building blocks of sequential logic circuits used in counters, memory, and data storage. This topic presents digital electronics aptitude questions and answers covering SR, JK, D, and T flip-flops with detailed explanations. Essential for GATE, DRDO, and BEL exam preparation, these MCQs help learners understand timing diagrams, truth tables, and applications in system design. By practicing these Flip-Flops questions with answers, you can master one of the most scoring areas in electronics and digital logic design.
Flips-Flops
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64 questions
41. What is one disadvantage of an S-R flip-flop?
- It has no enable input.
- It has an invalid state.
- It has no clock input.
- It has only a single output.
42. To completely load and then unload an 8-bit register requires how many clock pulses?
- 2
- 4
- 8
- 16
43. What is one disadvantage of an S-R flip-flop?
- It has no enable input.
- It has an invalid state.
- It has no clock input.
- It has only a single output.
44. Which of the following best describes the action of pulse-triggered FF's?
- The clock and the S-R inputs must be pulse shaped.
- The data is entered on the leading edge of the clock, and transferred out on the trailing edge of the clock.
- A pulse on the clock transfers data from input to output.
- The synchronous inputs must be pulsed.
45. An invalid condition in the operation of an active-HIGH input S-R latch occurs when ________.
- HIGHs are applied simultaneously to both inputs S and R
- LOWs are applied simultaneously to both inputs S and R
- a LOW is applied to the S input while a HIGH is applied to the R input
- a HIGH is applied to the S input while a LOW is applied to the R input
46. On a J-K flip-flop, when is the flip-flop in a hold condition?
- J = 0, K = 0
- J = 1, K = 0
- J = 0, K = 1
- J = 1, K = 1
47. Edge-triggered flip-flops must have:
- very fast response times.
- at least two inputs to handle rising and falling edges.
- a pulse transition detector.
- active-LOW inputs and complemented outputs.
48. As a general rule for stable flip-flop triggering, the clock pulse rise and fall times must be:
- very long.
- very short.
- at a maximum value to enable the input control signals to stabilize.
- of no consequence as long as the levels are within the determinate range of value.
49. A positive edge-triggered D flip-flop will store a 1 when ________.
- the D input is HIGH and the clock transitions from HIGH to LOW
- the D input is HIGH and the clock transitions from LOW to HIGH
- the D input is HIGH and the clock is LOW
- the D input is HIGH and the clock is HIGH
50. If an input is activated by a signal transition, it is ________.
- edge-triggered
- toggle triggered
- clock triggered
- noise triggered