Flips-Flops Questions and Answers
Flip-Flops are the fundamental building blocks of sequential logic circuits used in counters, memory, and data storage. This topic presents digital electronics aptitude questions and answers covering SR, JK, D, and T flip-flops with detailed explanations. Essential for GATE, DRDO, and BEL exam preparation, these MCQs help learners understand timing diagrams, truth tables, and applications in system design. By practicing these Flip-Flops questions with answers, you can master one of the most scoring areas in electronics and digital logic design.
Flips-Flops
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64 questions
31. A D flip-flop utilizing a PGT clock is in the CLEAR state. Which of the following input actions will cause it to change states?
- CLK = NGT, D = 0
- CLK = PGT, D = 0
- CLOCK NGT, D = 1
- CLOCK PGT, D = 1
32. In a 555 timer, three 5 k resistors provide a trigger level of ________.
- 1/4 VCC and a threshold level 1/2 VCC
- 1/3 VCC and a threshold level 3/4 VCC
- 1/3 VCC and a threshold level 2/3 VCC
- 1/4 VCC and a threshold level 2/3 VCC
33. Does the cross-coupled NOR flip-flop have active-HIGH or active-LOW set and reset inputs?
- active-HIGH
- active-LOW
34. The circuit that is primarily responsible for certain flip-flops to be designated as edge-triggered is the:
- edge-detection circuit.
- NOR latch.
- NAND latch.
- pulse-steering circuit.
35. With four J-K flip-flops wired as an asynchronous counter, the first output change of divider #4 indicates a count of how many input clock pulses?
- 16
- 8
- 4
- 2
36. What is the significance of the J and K terminals on the J-K flip-flop?
- There is no known significance in their designations.
- The J represents "jump," which is how the Q output reacts whenever the clock goes high and the J input is also HIGH.
- The letters were chosen in honor of Jack Kilby, the inventory of the integrated circuit.
- All of the other letters of the alphabet are already in use.
37. Why are the S and R inputs of a gated flip-flop said to be synchronous?
- They must occur with the gate.
- They occur independent of the gate.
38. Gated S-R flip-flops are called asynchronous because the output responds immediately to input changes.
- TRUE
- FALSE
39. Which of the following is not generally associated with flip-flops?
- Hold time
- Propagation delay time
- Interval time
- Set up time
40. Edge-triggered flip-flops must have:
- very fast response times
- at least two inputs to handle rising and falling edges
- positive edge-detection circuits
- negative edge-detection circuits