Electronic Devices and Circuit Theory-Field-Effect Transistors Questions and Answers

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Field-Effect Transistors (FETs) are core components in modern electronic circuits. This section includes field-effect transistors questions with answers curated for GATE, BEL, and DRDO electronics exams. Covering JFETs, MOSFETs, and their working principles, these aptitude questions and answers with explanations guide you through biasing, transfer characteristics, and amplifier design. Each solution includes step-by-step reasoning to strengthen your understanding of electronic device operation and enhance exam readiness.

Electronic Devices and Circuit Theory-Field-Effect Transistors

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11. A dual-gated MOSFET is

  • a depletion MOSFET.
  • an enhancement MOSFET.
  • a VMOSFET.
  • either a depletion or an enhancement MOSFET.
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12. What three areas are the drain characteristics of a JFET (VGS = 0) divided into?

  • ohmic, constant-current, breakdown
  • pinch-off, constant-current, avalanche
  • ohmic, constant-voltage, breakdown
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13. In a self-biased JFET circuit, if VD = VDD then ID = ________.

  • 0
  • cannot be determined from information above
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14. The resistance of a JFET biased in the ohmic region is controlled by

  • VD.
  • VGS.
  • VS.
  • VDS.
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15. The resistance of a JFET biased in the ohmic region is controlled by

  • VD.
  • VGS.
  • VS.
  • VDS.
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16. High input resistance for a JFET is due to

  • a metal oxide layer.
  • a large input resistor to the device.
  • an intrinsic layer.
  • the gate-source junction being reverse-biased.
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17. For a JFET, the change in drain current for a given change in gate-to-source voltage, with the drain-to-source voltage constant, is

  • breakdown.
  • reverse transconductance.
  • forward transconductance.
  • self-biasing.
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18. A JFET data sheet specifies VGS(off) = –6 V and IDSS = 8 mA. Find the value of ID when VGS = –3 V.

  • 2 mA
  • 4 mA
  • 8 mA
  • none of the above
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19. A JFET data sheet specifies VGS(off) = –10 V and IDSS = 8 mA. Find the value of ID when VGS = –3 V.

  • 2 mA
  • 1.4 mA
  • 4.8 mA
  • 3.92 mA
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20. If VD is less than expected (normal) for a self-biased JFET circuit, then it could be caused by a(n)

  • open RG.
  • open gate lead.
  • FET internally open at gate.
  • all of the above
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